Integrated circuit testing system and method

ABSTRACT

A system and method for testing the data propagation time in an integrated circuit at relatively low speed is described herein. The method uses at least two parallel circuits comprising a data circuit and a clock circuit, wherein these parallel circuits are provided with at least one inverter for sensing the feeding current of each circuit so as to obtain current pulses that are transformed into binary signals forwarded to a tester that measures the delay time between these signals.

FIELD OF THE INVENTION

[0001] The present invention relates to integrated circuits (ICs)testing. More specifically, the present invention is concerned withintegrated circuits delay testing system and method.

BACKGROUND OF THE INVENTION

[0002] Conventionally, a number of integrated circuits are formed on asingle wafer. The wafer is scribed along unused channels betweenintegrated circuits so that each integrated circuit can be broken off,or otherwise separated, from the wafer. Finally, each integrated circuitis individually packed in an integrated circuit package.

[0003] Generally, the integrated circuits are tested before the wafersare broken and also following the packaging. Important tests that theintegrated circuits typically have to pass following the packaginginclude delay tests, which are designed to verify that the circuitsperform at the desired speed. Indeed, the ICs should operate at a clockfrequency as determined in their specifications.

[0004] As a general trend, with the evolution of IC technology, the timedelays of the integrated circuits decrease, which means that thepropagation time of the pulses get smaller, resulting in a need for evermore precise, and most of all faster, measurements testers forperforming time delay tests.

[0005] Several methods are commonly employed for testing the speed ofintegrated circuits. One such method consists in testing thefunctionalities of the circuits at the highest frequency they cantolerate. However, this approach involves the use of high-speed testers,which are expensive devices that must be frequently replaced as the ICtechnology evolves.

[0006] Built-in self-test methods are commonly developed for testingintegrated circuits comprising embedded memory. Such methods providetesting facilities included by design into the circuits. However, sincethey result in larger surfaces of circuits and require additionalsophisticated tools, such methods are not as often used with circuitscomprising logic circuitry.

[0007] Integrated circuits comprising logic circuitry such as thoseusing complementary metal oxide semiconductor (CMOS) logic circuitry arewidely used in the fabrication of microprocessors, application specificintegrated circuits (“ASICs”) and memory storage areas.

[0008] Generally stated, the CMOS technology involves connectingp-channel MOS (for “metal oxide semiconductor”) transistor networks andn-channel MOS transistor networks together into a MOS or IC device. Theresulting devices, referred to as CMOS, are characterized by a decreasedstatic dissipation of power, since they require very little current tooperate in their steady state. Indeed, CMOS circuits only require powerwhen their state is altered. CMOS are thus especially useful in thefield of battery powered portable devices.

[0009] However, it is a shared concern in the art that the packagingstep of ICs adds considerably to their manufacturing cost. Efforts havetherefore been made in order to increase the level of testing ICs whilethey are still on the wafer, before even proceeding to the packagingstep.

[0010] There is obviously room for improvement in the art, in relationto means for simply and cost effectively performing delay tests whilethe ICs are still on the wafer.

OBJECTS OF THE INVENTION

[0011] An object of the present invention is therefore to provide animproved integrated circuit testing system and method.

SUMMARY OF THE INVENTION

[0012] More specifically, according to an aspect of the presentinvention, there is provided a system for testing the propagation timeof an integrated circuit; said testing system comprising:

[0013] a clock sensing circuit monitoring a clock signal of theintegrated circuit; said clock sensing circuit generating a sensed clocksignal;

[0014] a data sensing circuit monitoring a state transition at an inputof a receiving latch of the integrated circuit; said data sensingcircuit generating a sensed data signal;

[0015] wherein the propagation time of data through the integratedcircuit is calculated by determining delays between said sensed clocksignal and said sensed data signal.

[0016] According to another aspect of the present invention, there isprovided a method for testing the propagation time of an integratedcircuit; said method comprising the acts of:

[0017] generating a sensed clock signal corresponding to statetransitions of a clock signal of the integrated circuit;

[0018] generating a sensed data signal corresponding to statetransitions of the data present at an input of a receiving latch of theintegrated circuit;

[0019] measuring the propagation time of data through the integratedcircuit by calculated delays between the sensed clock signal and thesensed data signal.

[0020] Other objects, advantages and features of the present inventionwill become more apparent upon reading of the following non-restrictivedescription of preferred embodiments thereof, given by way of exampleonly with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In the appended drawings.

[0022]FIG. 1 schematically illustrates a conventional CMOS circuit;

[0023]FIG. 2 is a diagram of the propagation of a signal from point A topoint B of the circuit of FIG. 1, given a clock signal, versus time;

[0024]FIG. 3 schematically illustrates a CMOS circuit including a testcircuit according to an embodiment of the present invention;

[0025]FIG. 4 is a diagram of the propagation of a signal in the CMOScircuit of FIG. 3, given a clock signal, versus time; and

[0026]FIG. 5 is a diagram of an interface circuit, according to anaspect of the present invention.

DESCRIPTION OF AN EMBODIMENT

[0027] In a nutshell, the general concept of the present invention is toprovide a test capability, off-line, partly built-in or built-in, in anintegrated circuit, which allows testing the circuit at low speed andassessing the delay and synchronization times of the circuit at an earlystage of the testing process.

[0028] As is known in the art and schematically illustrated in FIG. 1,an integrated circuit 10 based on combinatorial principle, such as aCMOS, usually includes at least one clock domain (labeled CLK), so thatwhenever a clock signal 12 goes through a transition, a data signal 14is sent from the output Q of a transmitter latch 16 (point A) to theinput D of a receiving latch 18 (point B) through combinatory logic 20.

[0029] As illustrated in FIG. 2, there is a delay “t_(l)” between thebeginning time “T₁” of the clock signal transition 22 and the startingtime “T′₁” of the signal propagation from point A. Moreover, the signaltakes a time to reach point B. Generally stated, the signal takes a time“T_(p)”, hereinafter referred to as the propagation time, after thesignal transition 22 to reach the point B.

[0030] Moreover, generally, in order for the signal to be received in astable state at the input D of the receiving latch 18 of FIG. 1 and toavoid metastability of latches, it is required that the signal arrivesat point B a certain time “ΔT” before the starting time “T₂” of the nextclock signal transition, referred to as 22′ in FIG. 2. Therefore, theperiod of the clock, that is, for example as shown in FIG. 2, the timebetween two consecutive low-to-high transitions 22 and 22′ (at times T₁and T₂ respectively) of the clock signal 12, and the propagation time ofthe signal from the latch 16 to point B, contribute to determine theminimum time ΔT possible to achieve a stable signal state at the input Dof the receiving latch 18 of FIG. 1.

[0031] As will be understood by one skilled in the art, the propagationtime of the signal, i.e. the value of T_(p), is independent of the clockspeed. Therefore, the propagation time of the signal can be determinedat any clock speed, and advantageously at a lower clock speed, allowingthe use of low-speed testers. The goal is therefore to be able to detectwith sufficient precision the state change of the clock and the statechange at point B to enable the determination of T_(p).

[0032] Thus, a general concept of the present invention is to provideparallel circuits that transform changes of state, at predeterminedpoint, into instantaneous current pulses so as to create parallelcurrent circuits that do not interfere with the normal behavior of theIC. By transforming these current pulses into voltage pulses and byfeeding these voltage pulses to a conventional tester, it is possible todetermine T_(p) and therefore to test the delay of the circuit at lowerclock speed than the clock speed rating of the circuit.

[0033] An aspect of the present invention involves the use of invertersas sensors of change of state, as will be described hereinbelow.

[0034] Turning now to FIGS. 3 to 5 of the appended drawings, anembodiment of the method for ICs testing in accordance with the presentinvention will be described.

[0035] Generally illustrated in FIG. 3, the CMOS circuit 26 includes, incontrast to that of FIG. 1, a test circuit. The test system essentiallyconsists in setting two parallel circuits: a clock sensor circuit 28 anda data sensor circuit 30, so as to allow the separate monitoring of thetransition of two signals, namely the clock and the data at the input Dof the receiving latch 18. The sensor circuits 28 and 30 generate twosignals, namely the sensed clock signal (“S_CLOCK”), and the sensed datasignal (“S_DATA”).

[0036] Voltage-to-current converters 32 are inserted at the input of thedata latch 16, and at the end of the distribution network of the clocksignal. At least two circuits of converters are thus created, one(labeled 30) for monitoring the data signal, and the other one (labeled28) for monitoring the clock signal.

[0037] In the circuits 28 and 30, a transition is transformed into apulse of current by means of a voltage to current converters 32.

[0038] Inverters are used as voltage to current converters 32 in FIG. 3to detect change of states. Therefore, only their “VDD” supply port 32′and their ground port “GND” 32″ are considered, while their respectiveoutputs 33 are disregarded. These inverters sense the current in thefeed line of each one of the two parallel circuits 28 and 30, andprovide current pulses corresponding to transitions. Indeed, one skilledin the art will understand that since the inverters use CMOS technology,they consume power only when a change of state occurs at their input.This power consumption generates detectable pulses of current.

[0039]FIG. 4 shows a simplified representation of the current signal ofthe clock (“S_CLK”) and of the signal (“S_DATA”) from the latches comingfrom the sensors. The propagation T_(p) of the signal determines thedelay of the circuit. Knowing the time ΔT required for the data to bestable at the next clock pulse, one may thus determine the fastest clockspeed that may be used with the circuit 26.

[0040] Moreover, the width W of the current pulse corresponding to atransition of the clock is a measure of the synchronization bias, i.e.an evaluation of the time of propagation of the clock signal, due to thedistribution network.

[0041] In case there is a need for wider current pulses W, it ispossible to insert more than one inverter in series as a load to thefirst inverter so as to increase the duration of the current pulse.

[0042] Additionally, it is possible to minimize the current consumptionwhen the circuit is in a normal operating mode, by using transmissiongates (not shown) between the points to be tested and the first inverter32. These gates being controllable to put the inverters 32 in thecircuit only during the testing of the circuit.

[0043] As shown in FIG. 5, an interface 36 is provided between thecircuit to be tested 26 and a tester 38. The interface 36 monitors thefeed line of the inverters 32 and changes the current pulses from theinverters 32 into binary signals forwarded to the conventional tester38.

[0044] As seen in FIG. 5, four signals, i.e. VDD_S_data, GND_S_DATA,VDD_S_CLK and GND_S_CLK are supplied to the interface 36. Two separatebut similar amplification stages comprising operational amplifiers 40are used to transform the current pulses into voltage pulses detectableby the tester 38.

[0045] Such interface 36 may be integrated to the circuit of the tester38, or be external to the tester 38 as shown in FIG. 5.

[0046] It is also possible to integrate an interface 36 in the circuitto be tested 26 to enable a direct connection to the external tester 38for measuring the delays between the pulses. In that case, part of thetester 38 that tests the delay can also be integrated into the circuit26.

[0047] The tester 38 assesses the delay time between the binary signals(labeled DELAY) corresponding to the data and the binary signal (labeledREF) associated with the clock, i.e. the delay time between thebeginning of a clock transition and the end of a data signal. This delaytime precisely corresponds to the allowed delay time to be assessed.

[0048] By way of example of the present invention, an experiment is setup in order to measure different delay times with the system and methodas disclosed herein. Inverters encountered in commercial IC are used asexternal sensors. An interface between the feed line of the invertersand the tester are used as described hereinabove. The delay timesmeasured by way of this set up are comparable to the delay timesobtained by means of a high-speed oscilloscope.

[0049] One skilled in the art will appreciate that such parallelcircuits of current generally do not interfere with the ICs normalbehavior. Usually, the inverters used in the test system describedhereinabove only induce a negligible stray capacitance compared to othersystems using multiplexers for instance.

[0050] It is to be noted that the inverters may be simple CMOSinverters, essentially made of two transistors.

[0051] An additional interesting feature is that the known ways of latchinsertion, (such as the LSSD of IBM scan chain), may be applied inmaking the present sensor circuit. Indeed, the present invention makesuse of scan latches.

[0052] Therefore, in an advantageous embodiment of the presentinvention, software devices are coupled to the system so as to enableautomation of the insertion of the inverters in the neighborhood of thelatches according to known methods such as the scan chain method, orLSSD by IBM. Although not essential to the invention, software tools arevery useful. Existing software devices can be easily adapted to thepresent application, in particular software initially designed for thepurpose of inserting of scanning latches.

[0053] As it will be apparent to one skilled in the art, the presentinvention enables sorting out integrated circuits that do not meet thefabrication specifications, at a very early stage in the testingprocess. Indeed, this selection takes place during the very first set oftests performed on the ICs, while they are still on the wafers, beforethey are even cut out and individually packaged. Thus, the presentinvention enables discarding defective circuits before they arepackaged, which results in great cost and time savings.

[0054] A further advantage of the present invention is that it allowsthe use of existing testers, which need not be high-speed testers, formeasuring delay times of the order of a few hundreds of picoseconds,instead of using high frequency (GHz) costly testers, as is required inconventional testing methods. For instance, a tester such as theIMS-XL60™ from Integrated Measurement System™ Inc., is characterized bya maximal frequency of 60 MHz, can be used for measuring relative delayswith a 100 ps resolution. Indeed, as described hereinabove, thepropagation delay T_(p) is independent of the clock speed.

[0055] It is therefore obvious that the present invention permits anextended lifetime of semiconductor testers, thus reducing considerablythe costs related to tests.

[0056] By permitting an early sorting out of defective ICs and the useof non-costly testers, and since it altogether provides means forextending the wear life of testers, the present invention contributes toimportant savings related to the tests of lCs.

[0057] It is found in practice that the present invention isstraightforwardly applicable to testing integrated circuits of the CMOStype. It may be integrated to the software used during the designprocess and can be performed with standard testers.

[0058] In keeping with one of the principal objects of the invention,the method disclosed hereinabove is well adapted to detect defectscausing delays in an integrated circuit without performing high-speedtests by means of expensive devices.

[0059] Although the present invention has been described hereinabove byway of preferred embodiments thereof, it can be modified, withoutdeparting from the spirit and nature of the subject invention as definedin the appended claims.

What is claimed is:
 1. A system for testing the propagation time of anintegrated circuit; said testing system comprising: a clock sensingcircuit monitoring a clock signal of the integrated circuit; said clocksensing circuit generating a sensed clock signal; a data sensing circuitmonitoring a state transition at an input of a receiving latch of theintegrated circuit; said data sensing circuit generating a sensed datasignal; wherein the propagation time of data through the integratedcircuit is calculated by determining delays between said sensed clocksignal and said sensed data signal.
 2. The testing system recited inclaim 1, wherein said clock sensing circuit includes an inverter forsensing a transition in the clock signal of the integrated circuit andfor generating a current pulse corresponding to the clock signaltransition.
 3. The testing system recited in claim 2, wherein said datasensing circuit includes an inverter for sensing a transition in thedata signal at the input of the receiving latch of the integratedcircuit and for generating a current pulse corresponding to the datasignal transition.
 4. The testing system recited in claim 3, furthercomprising an interface receiving the current pulses corresponding tothe sensed clock and data signals and transforming these current pulsesinto binary signals.
 5. The testing system recited in claim 4, whereinsaid interface is provided with an output configured to be read by aconventional circuit tester.
 6. A method for testing the propagationtime of an integrated circuit; said method comprising the acts of:generating a sensed clock signal corresponding to state transitions of aclock signal of the integrated circuit; generating a sensed data signalcorresponding to state transitions of the data present at an input of areceiving latch of the integrated circuit; measuring the propagationtime of data through the integrated circuit by calculated delays betweenthe sensed clock signal and the sensed data signal.
 7. The testingmethod of claim 6, wherein said sensed clock signal generating actincludes the sub-act of monitoring the state transitions of the clocksignal.
 8. The testing method of claim 7, wherein said clock signalmonitoring sub-act includes sensing a transition in the clock signal ofthe integrated circuit and wherein said sensed clock signal generatingact includes the sub-act of generating current pulses corresponding toclock signal transitions.
 9. The testing method of claim 8, wherein saidtransition sensing sub-act includes providing an inverter for sensingsaid transitions.
 10. The testing method of claim 8, wherein said senseddata signal generating act includes the sub-act of monitoring the statetransitions of the data present at the input of the receiving latch ofthe integrated circuit.
 11. The testing method of claim 10, wherein saidstate transition monitoring sub-act includes sensing a transition in thedata present at the input of the receiving latch of the integratedcircuit and wherein said sensed data signal generating act includes thesub-act of generating current pulses corresponding to transitions in thedata present at the input of the receiving latch.
 12. The testing methodof claim 11, wherein said data transition sensing sub-act includesproviding an inverter for sensing said transitions.
 13. The testingmethod recited in claim 11, wherein said measuring act includesreceiving the current pulses corresponding to the sensed clock and datasignals;
 14. The testing method recited in claim 13, wherein saidmeasuring act includes transforming the current pulses into binarysignals.
 15. The testing method recited in claim 14, wherein saidmeasuring act includes supplying the binary signals to a conventionalcircuit tester.